1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 satellite applications flow? (saf) is a trademark of intersil corporation. hs-6617rh-t radiation hardened 2k x 8 cmos prom intersils satellite applications flow tm (saf) devices are fully tested and guaranteed to 100krad total dose. these qml class t devices are processed to a standard ?ow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. the intersil hs-6617rh-t is a radiation hardened 16k cmos prom, organized in a 2k word by 8-bit format. the chip is manufactured using a radiation hardened cmos process, and is designed to be functionally equivalent to the hm-6617. synchronous circuit design techniques combine with cmos processing to give this device high speed performance with very low power dissipation. on chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structure, such as the hs-80c86rh. the output enable control ( g) simpli?es microprocessor system interfacing by allowing output data bus control, in addition to, the chip enable control. synchronous operation of the hs-6617rh-t is ideal for high speed pipe-lined architecture systems and also in synchronous logic replacement functions. speci?cations speci?cations for rad hard qml devices are controlled by the defense supply center in columbus (dscc). the smd numbers listed below must be used when ordering. detailed electrical speci?cations for the hs-6617rh-t are contained in smd 5962-95708. a hot-link is provided from our website for downloading . www.intersil.com/spacedefense/newsafclasst.asp intersils quality management plan (qm plan), listing all class t screening operations, is also available on our website. www.intersil.com/quality/manuals.asp features ? qml class t, per mil-prf-38535 ? radiation performance - gamma dose ( g ) 1 x 10 5 rad(si) - seu let 16mev/mg/cm 2 - sel let 100mev/mg/cm 2 ? field programmable nicrome fuse links ? low standby power 1.1mw max ? low operating power 137.5mw/mhz max ? fast access time 100ns max ? ttl compatible inputs/outputs ? synchronous operation ? on chip address latches, three-state outputs pinouts HS1-6617RH-T (sbdip), cdip2-t24 top view hs9-6617rh-t (flatpack), cdfp4-f24 top view ordering information ordering number part number temp. range ( o c) 5962r9570801tjc HS1-6617RH-T -55 to 125 hs1-6617rh/proto hs1-6617rh/proto -55 to 125 5962r9570801txc hs9-6617rh-t -55 to 125 hs9-6617rh/proto hs9-6617rh/proto -55 to 125 note: minimum order quantity for -t is 150 units through distribution, or 450 units direct. 1 2 3 4 5 6 7 8 9 10 11 12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 16 17 18 19 20 21 22 23 24 15 14 13 v dd a9 p g a10 q7 q5 q4 q3 a8 e q6 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd v dd a8 a9 p ? g a10 e q7 q6 q5 q4 q3 2 3 4 5 6 7 8 9 10 11 12 1 24 23 22 21 20 19 18 17 16 15 14 13 ? p must be hardwired at all times to v dd , except during programming. data sheet july 1999 file number 4608.1
2 functional diagram timing waveform truth table e g mode 0 0 enabled 0 1 output disabled 1 x disabled msb lsb 16 128 x 128 matrix gated row decoder latched address register register latched address gate column decoder programming, and data output control 16 16 16 16 16 16 16 e e e 8 a 4 a 4 e 8 1 of 8 7a 7 a 128 msb lsb p e g a10 a9 a8 a7 a5 a4 a6 a3 a2 a1 a0 q0 - q7 all lines positive logic: active high three state buffers: output active address latches & gated decoders: p = hardwired to v dd except during programming latch on falling edge of e gate on falling edge of g a high valid data telqx tglqx 1.5v 1.5v tghqz tglqv 1.5v 1.5v tehqz 1.5v 1.5v teleh tehel telqv telax tavel telel valid address 1.5v 1.5v tavqv valid addresses ts 3.0v 0v 0v 3.0v 0v 3.0v addresses data output g e q0 - q7 figure 1. read cycle hs-6617rh-t
3 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil semiconductor products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/or spec ifications at any time with- out notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is b elieved to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of th ird parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see web site http://www.intersil.com die characteristics die dimensions: (4166 m m x 6350 m m x 483 m m 25.4 m m) 164 x 250 x 19mils 1mil metallization: type: silicon - aluminum thickness: 13.0k ? 2k ? substrate potential: v dd backside finish: silicon passivation: type: silox (s i o 2 ) thickness: 8.0k ? 1k ? worst case current density: < 2.0e5 a/cm 2 process: ssajiiv-rh metallization mask layout hs-6617rh-t a2 (6) a1 (7) a0 (8) q0 (9) q1 (10) q2 (11) gnd (12) q3 (13) q4 (14) q5 (15) q6 (16) q7 (17) (20) g (19) a10 (18) e (5) a3 (4) a4 (3)a5 (2) a6 (1) a7 (24)v dd (23) a8 (22) a9 (21) p hs-6617rh-t
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